{"id":16689,"date":"2025-08-22T10:33:17","date_gmt":"2025-08-22T08:33:17","guid":{"rendered":"https:\/\/www.ficontec.com\/?p=16689"},"modified":"2025-10-01T08:33:52","modified_gmt":"2025-10-01T06:33:52","slug":"electro-optical-wafer-level-tester-double-sided","status":"publish","type":"post","link":"https:\/\/www.ficontec.com\/jp\/electro-optical-wafer-level-tester-double-sided\/","title":{"rendered":"WLT-D2 double-sided electro-optical wafer tester"},"content":{"rendered":"[spb_row wrap_type=”content-width” row_bg_type=”image” color_row_height=”content-height” bg_type=”cover” parallax_image_height=”content-height” parallax_image_movement=”fixed” parallax_image_speed=”0.5″ parallax_video_height=”window-height” parallax_video_overlay=”none” row_overlay_opacity=”0″ row_padding_vertical=”30″ row_padding_horizontal=”0″ row_margin_vertical=”0″ remove_element_spacing=”no” inner_column_height=”col-natural” width=”1\/1″ el_position=”first last”] [spb_text_block pb_margin_bottom=”no” pb_border_bottom=”no” width=”1\/1″ el_position=”first last”]\n

Double-sided Wafer-level Testing<\/span><\/h1>\n

Unlocking the 3D CPO architecture with our double-sided electro-optical wafer tester<\/span><\/span><\/h3>\n[\/spb_text_block] [spb_text_block pb_margin_bottom=”no” pb_border_bottom=”no” width=”1\/1″ el_position=”first last”]\n

\"\"<\/p>\n

ficonTEC\u2019s double-sided electro-optical wafer-level tester (WLT-D2) is a breakthrough solution purpose-built to meet the demands of vertically integrated photonic and electronic die stacks used in CPU, GPU and switch applications. Designed for compatibility with industry-standard ATE platforms<\/a> for semiconductor test, this tool uniquely enables simultaneous electrical and optical probing on opposing sides of the wafer, thus addressing the requirements of cutting-edge designs such as TSMC\u2019s COUPE (Compact Universal Photonic Engine)<\/a>.<\/p>\n

Key innovations include a custom slotted wafer chuck, dynamic alignment of a 200+ kg wafer stage and vertical fiber array unit (FAU) probes with 3D-printed micro-lens tips for edge or grating-coupled access. Integrated automation features such as wafer autoloading, ATE tip inspection and cleaning pads ensure high throughput and process reliability in manufacturing environments.<\/p>\n

Whether for wafer-level validation or volume production, this tester is central to realizing scalable co-packaged optics (CPO) in high-performance systems.<\/p>\n[\/spb_text_block] [\/spb_row] [blank_spacer height=”0px” spacer_id=”application-video” spacer_name=”Application Video” width=”1\/1″ el_position=”first last”] [spb_row wrap_type=”content-width” row_bg_type=”color” row_bg_color=”#4e4f50″ color_row_height=”content-height” bg_type=”cover” parallax_image_height=”content-height” parallax_image_movement=”fixed” parallax_image_speed=”0.5″ parallax_video_height=”window-height” parallax_video_overlay=”none” row_overlay_opacity=”0″ row_padding_vertical=”80″ row_padding_horizontal=”0″ row_margin_vertical=”0″ remove_element_spacing=”no” inner_column_height=”col-natural” width=”1\/1″ el_position=”first last”] [spb_text_block pb_margin_bottom=”no” pb_border_bottom=”no” width=”1\/1″ el_position=”first last”]\n

Double-sided testing in action<\/span><\/h2>\n

<\/a><\/p>\n[\/spb_text_block] [\/spb_row] [spb_row wrap_type=”content-width” row_bg_type=”image” row_bg_color=”#f2f2f2″ color_row_height=”content-height” bg_image=”16923″ bg_type=”cover” parallax_image_height=”content-height” parallax_image_movement=”stellar” parallax_image_speed=”0.5″ parallax_video_height=”window-height” parallax_video_overlay=”none” row_overlay_opacity=”50″ row_padding_vertical=”30″ row_padding_horizontal=”0″ row_margin_vertical=”0″ remove_element_spacing=”no” inner_column_height=”col-natural” width=”1\/1″ el_position=”first last”] [blank_spacer height=”30px” width=”1\/1″ el_position=”first last”] [spb_text_block pb_margin_bottom=”no” pb_border_bottom=”no” width=”1\/1″ el_position=”first last”]\n

Key highlights:<\/span><\/h2>\n