Double-sided Wafer-level Testing
Unlocking the 3D CPO architecture with our double-sided electro-optical wafer tester
ficonTEC’s double-sided electro-optical wafer-level tester (WLT-D2) is a breakthrough solution purpose-built to meet the demands of vertically integrated photonic and electronic die stacks used in CPU, GPU and switch applications. Designed for compatibility with industry-standard ATE platforms for semiconductor test, this tool uniquely enables simultaneous electrical and optical probing on opposing sides of the wafer, thus addressing the requirements of cutting-edge designs such as TSMC’s COUPE (Compact Universal Photonic Engine).
Key innovations include a custom slotted wafer chuck, dynamic alignment of a 200+ kg wafer stage and vertical fiber array unit (FAU) probes with 3D-printed micro-lens tips for edge or grating-coupled access. Integrated automation features such as wafer autoloading, ATE tip inspection and cleaning pads ensure high throughput and process reliability in manufacturing environments.
Whether for wafer-level validation or volume production, this tester is central to realizing scalable co-packaged optics (CPO) in high-performance systems.
Double-sided testing in action
Key highlights:
-
Hard-dock ATE integration retains electrical probing on the top-side of the wafer
-
A precision 4-axis motion system establishes precision dynamic positioning of the wafer for electrical probing
-
A custom 300 mm wafer chuck is slotted to match the I/O pitch across the wafer, providing optical access from below
-
A high-precision 6–axis alignment engine below the chuck provides positioning of the optical probe
-
3D printed custom FAU optical probes with refractive beam-steering
Additional features:
-
Retractable slim-profile vision system for wafer referencing
-
Electrical probe tip inspection and cleaning
-
Compatibility with wafer autoloader
Require more details on double-sided wafer compatibility, or looking for volume testing at die or module level? Get in touch:
Contact us Request form
